Describe the bug
The vand_s64 intrinsic says it compiles to AND Dd,Dn,Dm.
|
int64x1_t vand_s64(int64x1_t a, int64x1_t b) a -> Dn;b -> Dm AND Dd,Dn,Dm Dd -> result v7/A32/A64 |
However, to my knowledge this instruction does not exist. There is no scalar variant documented:
https://developer.arm.com/documentation/ddi0602/2025-03/SIMD-FP-Instructions/AND--vector---Bitwise-AND--vector--
It is unsupported in LLVM 20.1.1:
> llvm-mc --version | head -n 1
Homebrew LLVM version 20.1.1
> echo 'and d0, d1, d2' | llvm-mc --arch=aarch64
<stdin>:1:5: error: invalid operand for instruction
and d0, d1, d2
^
Describe the bug
The
vand_s64intrinsic says it compiles toAND Dd,Dn,Dm.acle/tools/intrinsic_db/advsimd.csv
Line 1721 in c5d821b
However, to my knowledge this instruction does not exist. There is no scalar variant documented:
https://developer.arm.com/documentation/ddi0602/2025-03/SIMD-FP-Instructions/AND--vector---Bitwise-AND--vector--
It is unsupported in LLVM 20.1.1: