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Pull requests: llvm/circt

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Pull requests list

[ESI][Runtime] Add ChannelService for raw to_host/from_host channels ESI
#10072 opened Mar 28, 2026 by teqdruid Loading…
1
[Moore] Unify random builtins into urandom_range, add lowering Moore
#10071 opened Mar 27, 2026 by fabianschuiki Loading…
[ImportVerilog] Emit coroutines for tasks ImportVerilog
#10070 opened Mar 27, 2026 by fabianschuiki Loading…
3
[Moore] Add coroutine, call_coroutine ops; lower to LLHD Moore
#10069 opened Mar 27, 2026 by fabianschuiki Loading…
2
[FIRRTL] Add Domain Associations to Wires
#10065 opened Mar 27, 2026 by seldridge • Draft
1
[CoreToFSM] Require that all registers have the same reset signal
#10064 opened Mar 27, 2026 by TaoBi22 Loading…
1
[circt-reduce] Add domain field remover
#10062 opened Mar 27, 2026 by seldridge • Draft
1
[ImportVerilog] Handle $monitor([boh]?|on|off) statements ImportVerilog
#10057 opened Mar 27, 2026 by fabianschuiki Loading…
4
[circt-bmc] Include bound in violation and success messages
#10056 opened Mar 26, 2026 by AnmolM-777 Loading…
1
[circt-bmc] Include bound in violation and success messages
#10051 opened Mar 26, 2026 by AnmolM-777 Loading…
2
Conditonally add external attribute for memory element
#10050 opened Mar 26, 2026 by Abhilekhgautam Loading…
1
2
Bump LLVM to 80603c6672226cb48798bd60120c8f859dbeca19.
#10047 opened Mar 26, 2026 by mikeurbach Loading…
11
[FIRRTL][LowerToHW] Change InstanceChoice ABI from header files to defines
#10042 opened Mar 26, 2026 by uenoku Loading…
[FIRRTL] Improve domain port naming in InferDomains pass
#10037 opened Mar 25, 2026 by seldridge • Draft
[ExportVerilog] Add ModportType support for non-extern hw.module ports
#10030 opened Mar 25, 2026 by dmlockhart Loading…
2
[ExportVerilog] Fix XMR paths for inner symbols in generate.case (#9972)
#10025 opened Mar 24, 2026 by Salmooo Loading…
11
[FIRRTL] Invalids as constants in InferDomains
#10022 opened Mar 24, 2026 by seldridge • Draft
1
[HW] Add IMDCE module rewrites
#10007 opened Mar 22, 2026 by stomfaig Loading…
4
[HWFlattenModules] Add support for verif.formal parent ops.
#9984 opened Mar 19, 2026 by dobios • Draft
2
[RTG][circt-tblgen] Use config vars for include paths RTG Involving the `rtg` dialect
#9982 opened Mar 19, 2026 by maerhart Loading…
1
1
[Handshake] Fix argument index tracking with multiple ext memref args
#9978 opened Mar 19, 2026 by TopiLeppanen Loading…
1
[Sim][SimToSv] DPI-C Semantic preserving sim.func.dpi and sim.func.dpi.call
#9977 opened Mar 19, 2026 by pscabot Loading…
4
[FIRRTL] Emit memory initialization metadata FIRRTL Involving the `firrtl` dialect
#9974 opened Mar 18, 2026 by fzi-hielscher Loading…
1
[Datapath] Implement Add with Carry-In to Improve Subtraction Circuit Implementation
#9949 opened Mar 16, 2026 by sarthakmangla1 • Draft
1 task
8
[ImportVerilog][Sim] Added remaining Moore instructions for dynamic arrays, as well as the corresponding Sim dialect instructions
#9944 opened Mar 15, 2026 by yuriyKulinchenko Loading…
1
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