netlist

A Python library for parsing and analyzing electronic circuit netlists, with focus on Altium Designer format.

Description

A netlist describes all the electrical connections between components on a Printed Circuit Board (PCB). This library parses netlists and provides utilities for analyzing connectivity, finding pins, and performing automated checks.

Supported formats: - Altium Designer netlists - Other similar netlist formats

Installation

Install using pip:

pip install netlist

Or for development:

pip install -e .

Requirements: Python 3.8 or higher (tested up to Python 3.16)

Quick Start

Basic usage:

from python_netlist import Netlist

# Parse a netlist file
nl = Netlist('my_board.net')

# Check for orphaned nets (nets with <2 connections)
orphans = nl.check_orphans()

# Find pins on a specific net
pins = nl.find_pins('VCC', connector_map)

Features

Net Parsing

Parse netlist files to extract component connections and signal information.

Pin Finding

Map net names to physical connector pins using connector definitions.

Automated Checks

Detect common schematic errors like unconnected pins and orphaned nets.

Command-line Interface

Analyze netlists directly from the terminal.

Netlist Format

A typical Altium Designer generated netlist looks like this:

Wire List

<<< Component List >>>
100Ohms                         R1             0402
1uF                             C10            1206

<<< Wire List >>>

  NODE  REFERENCE  PIN #   PIN NAME       PIN TYPE    PART VALUE

[00002] VCC
        R1         1                      PASSIVE     myresistor
        C10        2                      PASSIVE     mycap

[00001] GND
        R1         2                      PASSIVE     myresistor
        C10        1                      PASSIVE     mycap

The netlist contains:

1. A basic BOM (value, designator, package)
2. A list of all signal names and their connections

Note: This module focuses on net connectivity and ignores the BOM section.

SOM Connection Helper

For large System On Module (SOM) designs, it can be tedious and error-prone to manually define signal connections in device trees or FPGA hardware designs.

Using the find_pins function, you can retrieve pin names based on net names.

Connector Definition Example

Define your module connectors and pins:

pz_pins = {
    "JX1": {
        "9": "R19",
        "10": "T19",
        "11": "T11",
        "12": "T12",
        "13": "T10",
        "14": "U12",
    },
    "JX2": {
        "13": "G14",
        "14": "J15",
        "17": "C20",
        "18": "B19",
    },
}

In this example: - The SOM has 2 connector parts: JX1 and JX2 - Pin 9 of connector JX1 maps to internal pin R19

Single-Part Component Example

Works for components with a single part (showing first 2 pins):

stm32f407_64_pins = {
    "1": "VBAT",
    "2": "PC13",
}

Automatic Checks

Catch common schematic capture mistakes by analyzing the netlist.

Orphan Detection

The check_orphans function lists all nets with fewer than 2 connections (configurable), which often indicates connection errors:

orphans = netlist.check_orphans(min_connections=2)

Command-Line Tool

Invoke the command-line tool:

python -m netlist --help

Use the built-in help to learn about available commands and options.

License

MIT License - see LICENSE.txt for details

Links

• Repository: https://github.com/chmousset/python-netlist