I'm making a hardware implementation of the classic RRT algorithm to learn Verilog and hardware design!
So far, I have built a simple visualization and a CPU implementation in Rust. The Verilog implementation is in progress!
| Name | Name | Last commit date | ||
|---|---|---|---|---|
I'm making a hardware implementation of the classic RRT algorithm to learn Verilog and hardware design!
So far, I have built a simple visualization and a CPU implementation in Rust. The Verilog implementation is in progress!